The technical field relates generally to computer architecture and more particularly, but not by way of limitation, to a method and apparatus for testing a simulated integrated circuit chip""s response to input propagation delays by emulating delays throughout a tolerance range.
Elements or components of a circuit are electrically interconnected by links. For example, on a circuit board, integrated circuit (IC) chips may be connected using links, or cables. Data may be sent to a chip in a data slice, or bundle, along with a data strobe. The data strobe is used to indicate that the accompanying data is valid. The recipient latches the data as soon as it sees the strobe. The length of these links may create a propagation delay in the transfer of data, which creates a potential problem for the chip receiving the data. This is particularly a problem with synchronous links where the protocol allows a phase of a signal to cross a synchronous boundary.
A chip may be designed to recognize and properly respond to link delays within a certain, specified tolerance range. In order to ensure that the chip properly processes data from delayed source synchronous links, it is desirable to test the chip""s response to these delays. In this testing process, the simulated chip under test is also referred to as the application specific integrated circuit (ASIC). The ASIC is simulated at the hardware description level, also called the register transfer level (RTL). In particular, it is desirable to verify the ASIC""s response to source synchronous link delays throughout the entire tolerance range of delays in an efficient manner. Even more delay/slice combinations must be tested on those links with skewxe2x80x94that is, those links having multiple data slices. This is done to verify the functional design of the simulated chip.
Unfortunately, no means exists for efficiently testing the chip""s response to link delays throughout the tolerance range or for multiple data slices. Existing methods of testing rely upon statically defined transport delays at the hardware description level (RTL). These methods are not efficient, because they require iteratively changing the delay values, recompiling, and running the system to exercise various delay lengths. This unnecessarily consumes CPU time, disk space, and user time. What is needed is an efficient means of verifying a chip""s response to delays in source synchronous links throughout the tolerance range and in multiple combinations.
A method and apparatus are disclosed for verifying the functional design of a system""s response to propagation delays from the inputs of source synchronous links during testing. The system emulates propagation delays by receiving data slice from a source, applying a random or known delay to the data slice, and sending the delayed data slice to the chip under test. In one embodiment, multiple data slices having varying delay values may be used to test combinations of delays.
A programmable delay element is used to emulate the propagation delays. This is may be implemented at the hardware description level by receiving the data slice onto multiple data buses, applying a different delay to the data slice on each data bus, and sending the delayed data slices as inputs into a multiplexor. The multiplexor may have a selector input that determines which amount of delay to test. To test multiple data slices in combination, multiple multiplexors may be used.
In another embodiment, the delay may be emulated using a higher level programming language and creating a multidimensional array. In one dimension, the array receives different data slices, and in the other it assigns different delay values. The multidimensional array then receives multiple data slices at the same time. Each delay value is stored in a different array location, depending upon the delay assigned to the data slice. An output entry is sent to the chip under test. The array entries may be shifted each clock cycle to the output entry, or a pointer may be used to specify a different output entry each clock cycle.
FIG. 1 is a block diagram of the system.
FIG. 2 is a more detailed block diagram of the system of FIG. 1.
FIG. 3 is a block diagram of a system for testing more than one ASIC.
FIG. 4 is a flow chart of the method used by the system.
FIG. 5 is a block diagram showing a hardware description language implementation of the programmable delay element.
FIG. 6 is a flow chart of one implementation of the method.
FIGS. 7A through 7G show the progression of data slices through a matrix of a second implementation of the programmable delay element.